HD64F2145BTE20 Renesas Electronics America, HD64F2145BTE20 Datasheet - Page 378

• Manufacturer Part Number: HD64F2145BTE20
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of HD64F2145BTE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 13 Timer Connection
Bit
3
2
1
0
Legend:
X:
Table 13.2 Synchronization Signal Connection Enable
Bit 5
SCONE
0
1
Rev. 3.00 Mar 21, 2006 page 322 of 788
REJ09B0300-0300
Don’t care
Bit Name
HFINV
VFINV
HIINV
VIINV
Normal connection (Initial value)
Synchronization signal
connection mode
Mode
Initial Value
0
0
0
0
R/W
R/W
R/W
R/W
R/W
FTIA
input
IVI
signal
FTIA
Description
Input Synchronization Signal Inversion
These bits select inversion of the input phase of the
spare horizontal synchronization signal (HFBACKI),
the spare vertical synchronization signal (VFBACKI),
the horizontal synchronization signal (HSYNCI),
composite synchronization signal (CSYNCI), and the
vertical synchronization signal (VSYNCI).
0: The HFBACKI pin state is used directly as the
1: The HFBACKI pin state is inverted before use as
0: The VFBACKI pin state is used directly as the
1: The VFBACKI pin state is inverted before use as
0: The HSYNCI and CSYNCI pin states are used
1: The HSYNCI and CSYNCI pin states are inverted
0: The VSYNCI pin state is used directly as the
1: The VSYNCI pin state is inverted before use as the
HFBACKI input
the HFBACKI input
VFBACKI input
the VFBACKI input
directly as the HSYNCI and CSYNCI inputs
before use as the HSYNCI and CSYNCI inputs
VSYNCI input
VSYNCI input
HFINV
VFINV
HIINV
VIINV
Description
FTIB
FTIB
input
TMO1
signal
FTIC
FTIC
input
VFBACKI
input
FTID
FTID
input
IHI
signal
TMCI1
TMCI1
input
IHI
signal
TMRI1
TMRI1
input
IVI inverse
signal