HD64F2145BTE20 Renesas Electronics America, HD64F2145BTE20 Datasheet - Page 34

• Manufacturer Part Number: HD64F2145BTE20
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of HD64F2145BTE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

16.5 Interrupt Sources............................................................................................................... 475
16.6 Usage Notes ...................................................................................................................... 475
Section 17 Keyboard Buffer Controller
17.1 Features ............................................................................................................................. 489
17.2 Input/Output Pins .............................................................................................................. 491
17.3 Register Descriptions ........................................................................................................ 492
17.4 Operation .......................................................................................................................... 496
17.5 Usage Notes ...................................................................................................................... 508
Section 18 Host Interface X-Bus Interface (XBS)
18.1 Features ............................................................................................................................. 509
18.2 Input/Output Pins .............................................................................................................. 511
18.3 Register Descriptions ........................................................................................................ 512
18.4 Operation .......................................................................................................................... 519
18.5 Interrupt Sources............................................................................................................... 525
Rev. 3.00 Mar 21, 2006 page xxxii of liv
16.4.11 Initialization of Internal State .............................................................................. 473
16.6.1 Module Stop Mode Setting .................................................................................. 488
17.3.1 Keyboard Control Register H (KBCRH) ............................................................. 492
17.3.2 Keyboard Control Register L (KBCRL) .............................................................. 494
17.3.3 Keyboard Data Buffer Register (KBBR) ............................................................. 495
17.4.1 Receive Operation................................................................................................ 496
17.4.2 Transmit Operation .............................................................................................. 497
17.4.3 Receive Abort ...................................................................................................... 500
17.4.4 KCLKI and KDI Read Timing............................................................................. 503
17.4.5 KCLKO and KDO Write Timing......................................................................... 504
17.4.6 KBF Setting Timing and KCLK Control ............................................................. 505
17.4.7 Receive Timing.................................................................................................... 506
17.4.8 KCLK Fall Interrupt Operation............................................................................ 507
17.5.1 KBIOE Setting and KCLK Falling Edge Detection............................................. 508
17.5.2 Module Stop Mode Setting .................................................................................. 508
18.3.1 System Control Register 2 (SYSCR2) ................................................................. 512
18.3.2 Host Interface Control Register (HICR) Host Interface Control Register 2
18.3.3 Input Data Register (IDR).................................................................................... 517
18.3.4 Output Data Register 1 (ODR)............................................................................. 517
18.3.5 Status Register (STR) .......................................................................................... 518
18.4.1 Host Interface Activation ..................................................................................... 519
18.4.2 Control States....................................................................................................... 521
18.4.3 A20 Gate .............................................................................................................. 521
18.4.4 Host Interface Pin Shutdown Function ................................................................ 523
(HICR2) ............................................................................................................... 514
........................................................................ 489
..................................................... 509