HD64F2145BTE20 Renesas Electronics America, HD64F2145BTE20 Datasheet - Page 152

• Manufacturer Part Number: HD64F2145BTE20
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of HD64F2145BTE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 5 Interrupt Controller
5.3.5
IER controls the enabling and disabling of interrupt requests IRQ7 to IRQ0.
Bit
7
6
5
4
3
2
1
0
5.3.6
The ISR register is a flag register that indicates the status of IRQ7 to IRQ0 interrupt requests.
Bit
7
6
5
4
3
2
1
0
Notes: 1. When a product, in which a DTC is incorporated, is used, the corresponding flag bit is
Rev. 3.00 Mar 21, 2006 page 96 of 788
REJ09B0300-0300
2. Only 0 can be written, for flag clearing.
Bit Name
IRQ7E
IRQ6E
IRQ5E
IRQ4E
IRQ3E
IRQ2E
IRQ1E
IRQ0E
Bit Name
IRQ7F
IRQ6F
IRQ5F
IRQ4F
IRQ3F
IRQ2F
IRQ1F
IRQ0F
IRQ Enable Register (IER)
IRQ Status Register (ISR)
not automatically cleared even when exception handing is executed. For details, refer to
section 5.8.4, Setting on a Product Incorporating DTC.
Initial Value
0
0
0
0
0
0
0
0
Initial Value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/(W) *
2
2
2
2
2
2
2
2
Description
IRQn Enable (n = 7 to 0)
The IRQn interrupt request is enabled when this
bit is 1.
Description
[Setting condition]
When the interrupt source selected by the ISCR
registers occurs
[Clearing conditions]
When reading IRQnF flag when IRQnF = 1,
then writing 0 to IRQnF flag
When interrupt exception handling is
executed when low-level detection is set
and IRQn input is high (n = 7 to 0) *
When IRQn interrupt exception handling is
executed when falling-edge, rising-edge, or
both-edge detection is set *
1
1