HD64F2145BTE20 Renesas Electronics America, HD64F2145BTE20 Datasheet - Page 218

• Manufacturer Part Number: HD64F2145BTE20
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of HD64F2145BTE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 7 Data Transfer Controller (DTC)
Table 7.5
Mode
Normal
Repeat
Block transfer
N: Block size (initial setting of CRAH and CRAL)
Table 7.6
The number of execution states is calculated from using the formula below. Note that
of all transfers activated by one activation source (the number in which the CHNE bit is set to 1,
plus 1).
For example, when the DTC vector address table is located in on-chip ROM, normal mode is set,
and data is transferred from on-chip ROM to an internal I/O register, then the time required for the
DTC operation is 13 states. The time from activation to the end of data write is 10 states.
Rev. 3.00 Mar 21, 2006 page 162 of 788
REJ09B0300-0300
Bus width
Access states
Execution
status
Object to be Accessed
Number of execution states = I · S
Vector read
Register information
read/write
Byte data read
Word data read
Byte data write
Word data write
Internal operation S
DTC Execution Status
Number of States Required for Each Execution Status
Vector Read
I
1
1
1
S
S
S
S
S
S
I
J
K
K
L
L
M
Register Information
Read/Write
J
6
6
6
RAM
Chip
On-
32
—
1
1
1
1
1
1
I
+
ROM
Chip
On-
16
—
1
1
1
1
1
1
(J · S
On-Chip I/O
J
Registers
—
—
8
2
2
4
2
4
+ K · S
Data Read
K
1
1
N
16
K
—
—
2
2
2
2
2
+ L · S
1
—
L
2
4
2
4
2
4
) + M · S
Data Write
L
1
1
N
External Devices
8
6 + 2m
6 + 2m
6 + 2m
3 + m
3 + m
—
3
M
—
Internal
Operations
M
3
3
3
2
2
2
2
2
2
is the sum
16
3 + m
3 + m
3 + m
3 + m
3 + m
—
3