HD64F2145BTE20 Renesas Electronics America, HD64F2145BTE20 Datasheet - Page 25

• Manufacturer Part Number: HD64F2145BTE20
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of HD64F2145BTE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

5.4
5.5
5.6
5.7
5.8
Section 6 Bus Controller (BSC)
6.1
6.2
6.3
6.4
6.5
5.3.4
5.3.5
5.3.6
5.3.7
Interrupt Sources............................................................................................................... 100
5.4.1
5.4.2
Interrupt Exception Handling Vector Table...................................................................... 102
Interrupt Control Modes and Interrupt Operation ............................................................. 105
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
Address Break ................................................................................................................... 115
5.7.1
5.7.2
5.7.3
5.7.4
Usage Notes ...................................................................................................................... 118
5.8.1
5.8.2
5.8.3
5.8.4
5.8.5
Features ............................................................................................................................. 121
Input/Output Pins .............................................................................................................. 123
Register Descriptions ........................................................................................................ 123
6.3.1
6.3.2
Bus Control ....................................................................................................................... 126
6.4.1
6.4.2
6.4.3
6.4.4
Basic Bus Interface ........................................................................................................... 129
6.5.1
6.5.2
IRQ Sense Control Registers (ISCRH, ISCRL)................................................... 95
IRQ Enable Register (IER) .................................................................................. 96
IRQ Status Register (ISR).................................................................................... 96
Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR) and
Wake-Up Event Interrupt Mask Register (WUEMRB) ....................................... 97
External Interrupts ............................................................................................... 100
Internal Interrupts................................................................................................. 102
Interrupt Control Mode 0 ..................................................................................... 105
Interrupt Control Mode 1 ..................................................................................... 107
Interrupt Exception Handling Sequence .............................................................. 110
Interrupt Response Times .................................................................................... 112
DTC Activation by Interrupt................................................................................ 113
Features................................................................................................................ 115
Block Diagram ..................................................................................................... 115
Operation ............................................................................................................. 116
Usage Notes ......................................................................................................... 116
Conflict between Interrupt Generation and Disabling ......................................... 118
Instructions that Disable Interrupts ...................................................................... 119
Interrupts during Execution of EEPMOV Instruction.......................................... 119
Setting on Product Incorporating DTC ................................................................ 119
IRQ Status Register (ISR).................................................................................... 120
Bus Control Register (BCR) ................................................................................ 124
Wait State Control Register (WSCR) .................................................................. 125
Bus Specifications................................................................................................ 126
Advanced Mode................................................................................................... 127
Normal Mode....................................................................................................... 127
I/O Select Signals................................................................................................. 128
Data Size and Data Alignment............................................................................. 129
Valid Strobes........................................................................................................ 130
...................................................................................... 121
Rev. 3.00 Mar 21, 2006 page xxiii of liv