HD64F2145BTE20 Renesas Electronics America, HD64F2145BTE20 Datasheet - Page 692

• Manufacturer Part Number: HD64F2145BTE20
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of HD64F2145BTE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 24 Clock Pulse Generator
Table 24.3 External Clock Input Conditions
Item
External clock
input pulse width
low level
External clock
input pulse width
high level
External clock
rising time
External clock
falling time
Clock pulse width
low level
Clock pulse width
high level
The oscillator and duty correction circuit have a function to adjust the waveform of the external
clock input that is input to the EXTAL pin. When a specified clock signal is input to the EXTAL
pin, internal clock signal output is determined after the external clock output stabilization delay
time (t
signal should be set to low to hold it in reset state. Table 24.4 shows the external clock output
stabilization delay time. Figure 24.6 shows the timing of the external clock output stabilization
delay time.
Rev. 3.00 Mar 21, 2006 page 636 of 788
REJ09B0300-0300
DEXT
) has passed. As the clock signal output is not determined during the t
EXTAL
Symbol Min
t
t
t
t
t
t
EXL
EXH
EXr
EXf
CL
CH
t
EXr
Figure 24.5 External Clock Input Timing
V
40
40
—
—
0.4
80
0.4
80
CC
= 2.7 to 3.6 V
t
Max
—
—
10
10
0.6
—
0.6
—
EXH
V
Min
20
20
—
—
0.4
80
0.4
80
CC
= 5.0 V
t
EXf
t
EXL
Max
—
—
5
5
0.6
—
0.6
—
10
Unit
ns
ns
ns
ns
t
ns
t
ns
cyc
cyc
V
CC
× 0.5
Test Conditions
Figure 24.5
DEXT
< 5 MHz
5 MHz
5 MHz
5 MHz
cycle, a reset
Figure
28.6