HD64F2145BTE20 Renesas Electronics America, HD64F2145BTE20 Datasheet - Page 697

IC H8S MCU FLASH 256K 100-QFP

HD64F2145BTE20

Manufacturer Part Number
HD64F2145BTE20
Description
IC H8S MCU FLASH 256K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of HD64F2145BTE20

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
74
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
For operating modes after the reset state is cancelled, this LSI has not only the normal program
execution state but also seven power-down modes in which power dissipation is significantly
reduced. In addition, there is also module stop mode in which reduced power dissipation can be
achieved by individually stopping on-chip peripheral modules.
25.1
Power-down modes are controlled by the following registers. To access SBYCR, LPWRCR,
MSTPCRH, and MSTPCRL, the FLSHE bit in the serial timer control register (STCR) must be
cleared to 0. For details on STCR, see section 3.2.3, Serial Timer Control Register (STCR).
Medium-speed mode
System clock frequency for the CPU operation can be selected as /2, /4, /8, /16,or /32.
Subactive mode
The CPU operates based on the subclock and on-chip peripheral modules other than TMR_0,
TMR_1, WDT_0, and WDT_1 stop operating.
Sleep mode
The CPU stops but on-chip peripheral modules continue operating.
Subsleep mode
The CPU and on-chip peripheral modules other than TMR_0, TMR_1, WDT_0, and WDT_1
stop operating.
Watch mode
The CPU and on-chip peripheral modules other than WDT_1 stop operating.
Software standby mode
Clock oscillation stops, and the CPU and on-chip peripheral modules stop operating.
Hardware standby mode
Clock oscillation stops, and the CPU and on-chip peripheral modules enter reset state.
Module stop mode
Independently of above operating modes, on-chip peripheral modules that are not used can be
stopped individually.
Standby control register (SBYCR)
Low power control register (LPWRCR)
Module stop control register H (MSTPCRH)
Module stop control register L (MSTPCRL)
Register Descriptions
Section 25 Power-Down Modes
Rev. 3.00 Mar 21, 2006 page 641 of 788
Section 25 Power-Down Modes
REJ09B0300-0300

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