R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 1014

MCU 24KB FLASH 384K 144-LQFP

R5F61662N50FPV

Manufacturer Part Number
R5F61662N50FPV
Description
MCU 24KB FLASH 384K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61662N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61662N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 26 Electrical Characteristics
(5)
Table 26.8 Timing of On-Chip Peripheral Modules
Conditions: Vcc = PLLVcc = 3.0 to 3.6 V, AVcc = 3.0 to 3.6 V, AVccP = AVccA = AVccD = 3.0
Rev. 2.00 Sep. 16, 2009 Page 984 of 1036
REJ09B0414-0200
I/O ports Output data delay time
TPU
PPG
8-bit
timer
WDT
On-Chip Peripheral Modules
Input data setup time
Input data hold time
Timer output delay time
Timer input setup time
Timer clock input setup time
Timer clock
pulse width
Pulse output delay time
Timer output delay time
Timer reset input setup time
Timer clock input setup time
Timer clock
pulse width
Overflow output delay time
to 3.6 V, Vref = 3.0 V to AVcc, AVrefT = AVccA, Vss = PLLVss = AVss = AVssP =
AVssA = AVssD = AVrefB = 0 V
Bφ = 8 to 50 MHz, Ta = –20 to + 75 °C (regular specifications),
Ta = –40 to + 85 °C (wide-range specifications)
Item
Single-edge
setting
Both-edge
setting
Single-edge
setting
Both-edge
setting
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
PWD
PRS
PRH
TOCD
TICS
TCKS
TCKWH
TCKWL
POD
TMOD
TMRS
TMCS
TMCWH
TMCWL
WOVD
Min.
25
25
25
25
1.5
2.5
25
25
1.5
2.5
Max.
40
40
40
40
40
Unit
ns
ns
ns
ns
ns
ns
t
t
ns
ns
ns
ns
t
t
ns
cyc
cyc
cyc
cyc
Test Conditions
Figure 26.26
Figure 26.26
Figure 26.28
Figure 26.29
Figure 26.30
Figure 26.31
Figure 26.32
Figure 26.33

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