R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 785

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

19.4.3
In single mode, either normal single mode, in which A/D conversion is executed once for a
specified one analog input channel, or multi-channel mode, in which A/D conversion is executed
once for each of the multiple channels in sequence, can be selected. Specifying two or more
channels for A/D conversion by bits CH0 to CH5 in DSADCSR selects multi-channel mode
operation.
Figure 19.3 shows an example of ∆Σ A/D converter operation (in single-channel single mode with
channel 1 selected).
When only one channel is selected (normal single mode), A/D conversion is performed once in the
following way.
1. A/D conversion is started for the selected channel when the ADST bit in DSADCSR is set to 1
2. When A/D conversion is completed, the result is transferred to the ∆Σ A/D data register for the
3. When the result of A/D conversion is transferred to the data register and conversion by the ∆Σ
4. The ADST bit remains set to 1 during A/D conversion and is automatically cleared on
5. If the ADST bit is cleared to 0 during A/D conversion, the conversion is stopped and the ∆Σ
by software or by the input of trigger signal selected by the TRGS1 and TRGS0 bits in
DSADCSR.
selected channel (DSADDRn, n = 0 to 5).
A/D converter is complete, the ADF bit in DSADCSR is set to 1. If the ADIE bit in
DSADCSR is set to 1 at this time, a DSADI interrupt request is generated.
completion of A/D conversion. When the ADST bit is again set to 1, A/D conversion for the
selected channel is started again.
A/D converter enters the idle state.
Single Mode
Rev. 2.00 Sep. 16, 2009 Page 755 of 1036
Section 19 ∆Σ A/D Converter
REJ09B0414-0200