R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 405

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10.9.9
When overwriting of the DTC-transfer enable register (DTCER) and the generation of an interrupt
that is a source for DTC activation are in competition, activation of the DTC and interrupt
exception processing by the CPU will both proceed at the same time. Depending on the conditions
at this time, doubling of interrupts may occur. If there is a possibility of competition between
overwriting of DTCER and generation of an interrupt that is a source for DTC activation, proceed
with overwriting of DTCER according to the relevant procedure given below.
(corresponding bit = 1 in the CCR).
Restore the original value of the
Back-up the value of the CCR.
Set the interrupt-mask bit to 1
Points for Caution when Overwriting DTCER
Dummy-read the DTCER.
interrupt-control mode 0
Overwrite the DTCER.
interrupt-mask bit.
In the case of
Figure 10.17 Example of Procedures for Overwriting DTCER
END
Set the interrupt-request masking level to 7
Restore the original value of the
interrupt-request masking level.
Back-up the value of the EXR.
(in the EXR, I2, I1, I0 = B'111).
Dummy-read the DTCER.
interrupt-control mode 2
Overwrite the DTCER.
In the case of
Rev. 2.00 Sep. 16, 2009 Page 375 of 1036
Section 10 Data Transfer Controller (DTC)
END
REJ09B0414-0200
Interrupts are
masked