R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 792

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 19 ∆Σ A/D Converter
19.4.6
After the ADST bit in DSADCSR has been set to 1 to initiate conversion, the ∆Σ A/D converter
only starts sampling the analog inputs after the ∆Σ A/D converter start-up delay time (t
to wait for the ∆Σ modulator to be stabilized (t
analog input and converts it to a sequence of digital values, which is then passed through a digital
filter. The A/D conversion ends after the input sampling time (t
modulator stop delay time (t
Figure 19.8 shows the timing of A/D conversion, and tables 19.5 and 19.6 show A/D conversion
times. As shown in figure 19.8, the A/D conversion time is a total of four periods. t
vary because they are determined by the timing of synchronization between different clock signals
and the state of control of synchronization processing at the end of the previous round of A/D
conversion. For this reason, conversion times vary within the range shown in table 19.5.
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(1)
(2)
t
t
t
t
[Legend]
t
SD
SWT
SPLT
CONV
ED
internal reset signal
∆Σ modulator
Write signal
Input sampling
timing signal
Address
: DSADCSR write cycle
: Address of DSADCSR
: ∆Σ A/D converter start delay time
: ∆Σ modulator stabilization wait time
: Input sampling time
: ∆Σ A/D converter stop delay time
: A/D conversion time (first conversion)
Analog Input Sampling and A/D Conversion Time
ADST
Figure 19.8 A/D Conversion Timing (Single Mode, Once, One Channel)
ADF
(1)
(2)
t
ED
SD
) have elapsed.
t
SWT
SWT
) have elapsed. The ∆Σ modulator samples the
t
CONV
t
SPLT
SPLT
) and the subsequent ∆Σ
t
ED
SD
and t
SD
) and time
ED
can