R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 753

MCU 24KB FLASH 384K 144-LQFP

R5F61662N50FPV

Manufacturer Part Number
R5F61662N50FPV
Description
MCU 24KB FLASH 384K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61662N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61662N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
18.4
The A/D converter operates by successive approximation with 10-bit resolution. It has two
operating modes: single mode and scan mode. When configuring the A/D converter, first set the
clock for A/D conversion. Before changing the operating mode or analog input channel, clear the
ADST bit in ADCSR to 0 to stop A/D conversion to prevent incorrect operation. The ADST bit
can be set to 1 at the same time as the operating mode or analog input channel is changed.
18.4.1
In single mode, A/D conversion is to be performed only once on the analog input of the specified
single channel.
1. A/D conversion for the selected channel is started when the ADST bit in ADCSR is set to 1 by
2. When A/D conversion is completed, the A/D conversion result is transferred to the
3. When A/D conversion is completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set
4. The ADST bit remains set to 1 during A/D conversion, and is automatically cleared to 0 when
software, TPU, TMR, or an external trigger input.
corresponding A/D data register of the channel.
to 1 at this time, an ADI interrupt request is generated.
A/D conversion ends. The A/D converter enters wait state. If the ADST bit is cleared to 0
during A/D conversion, A/D conversion stops and the A/D converter enters wait state.
Operation
Single Mode
Rev. 2.00 Sep. 16, 2009 Page 723 of 1036
Section 18 A/D Converter
REJ09B0414-0200

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