R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 127

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.7
There are two instructions that cause exception handling: trap instruction and illegal instruction.
5.7.1
Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction
exception handling can be executed at all times in the program execution state. The trap
instruction exception handling is as follows:
1. The contents of PC, CCR, and EXR are saved in the stack.
2. The interrupt mask bit is updated and the T bit is cleared to 0.
3. An exception handling vector table address corresponding to the vector number specified in
A start address is read from the vector table corresponding to a vector number from 0 to 3, as
specified in the instruction code.
Table 5.8 shows the state of CCR and EXR after execution of trap instruction exception handling.
Table 5.8
[Legend]
1: Set to 1
0: Cleared to 0
: Retains the previous value.
Interrupt Control Mode
0
2
the TRAPA instruction is generated, the start address of the exception service routine is loaded
from the vector table to PC, and program execution starts from that address.
Instruction Exception Handling
Trap Instruction
States of CCR and EXR after Trap Instruction Exception Handling
I
1
1
CCR
UI


Rev. 2.00 Sep. 16, 2009 Page 97 of 1036
I2 to I0
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
Section 5 Exception Handling
EXR
REJ09B0414-0200
T

0