R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 593

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Notes: 1. To use an external reset or external clock, the DDR and ICR bits in the corresponding
Bit
6
5
4
3
2
1
0
2. In unit 2 and unit 3, one interrupt signal is used for CMIEB or CMIEA. For details, see
3. Available only in unit 0 and unit 1.
Bit Name
CMIEA
OVIE
CCLR1
CCLR0
CKS2
CKS1
CKS0
pin should be set to 0 and 1, respectively. For details, see section 11, I/O Ports.
section 14.7, Interrupt Sources.
Initial
Value
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Compare Match Interrupt Enable A
Selects whether CMFA interrupt requests (CMIA) are
enabled or disabled when the CMFA flag in TCSR is set
to 1. *
0: CMFA interrupt requests (CMIA) are disabled
1: CMFA interrupt requests (CMIA) are enabled
Timer Overflow Interrupt Enable*
Selects whether OVF interrupt requests (OVI) are
enabled or disabled when the OVF flag in TCSR is set to
1.
0: OVF interrupt requests (OVI) are disabled
1: OVF interrupt requests (OVI) are enabled
Counter Clear 1 and 0*
These bits select the method by which TCNT is cleared.
00: Clearing is disabled
01: Cleared by compare match A
10: Cleared by compare match B
11: Cleared at rising edge (TMRIS in TCCR is cleared to
Clock Select 2 to 0*
These bits select the clock input to TCNT and count
condition. See table 14.2.
0) of the external reset input or when the external
reset input is high (TMRIS in TCCR is set to 1) *
2
Rev. 2.00 Sep. 16, 2009 Page 563 of 1036
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Section 14 8-Bit Timers (TMR)
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REJ09B0414-0200
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