R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 393

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10.5.6
In block transfer mode, one operation transfers one block of data. Either the transfer source or the
transfer destination is designated as a block area by the DTS bit in MRB.
The block size is 1 to 256 bytes (1 to 256 words, or 1 to 256 longwords). When the transfer of one
block ends, the block size counter (CRAL) and address register (SAR when DTS = 1 or DAR
when DTS = 0) specified as the block area is restored to the initial state. The other address register
is then incremented, decremented, or left fixed. From 1 to 65,536 transfers can be specified. When
the specified number of transfers ends, an interrupt is requested to the CPU.
Table 10.8 lists the register function in block transfer mode. Figure 10.9 shows the memory map
in block transfer mode.
Table 10.8 Register Function in Block Transfer Mode
Note:
Register Function
SAR
DAR
CRAH
CRAL
CRB
*
Block Transfer Mode
Source address
Destination address
Block size storage
Block size counter
Block transfer counter
Transfer information writeback is skipped.
SAR
(When Transfer Destination is Specified as Block Area)
Figure 10.9 Memory Map in Block Transfer Mode
Transfer source data area
Nth block
1st block
:
:
Written Back Value
DTS =0: Incremented/decremented/fixed*
DTS = 1: SAR initial value
DTS = 0: DAR initial value
DTS =1: Incremented/decremented/fixed*
CRAH
CRAH
CRB − 1
Transfer
Transfer destination data area
(specified as block area)
Rev. 2.00 Sep. 16, 2009 Page 363 of 1036
Section 10 Data Transfer Controller (DTC)
Block area
DAR
REJ09B0414-0200