R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 735

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.4.5
In slave receive mode, the master device outputs the transmit clock and the transmit data, and the
slave device returns an acknowledge signal. Figures 17.11 and 17.12 show the operation timings
in slave receive mode. The reception procedure and operations in slave receive mode are described
below.
1. Set the ICR bit in the corresponding register to 1. Then, set the ICE bit in ICCRA to 1. Set the
2. When the slave address matches in the first frame following detection of the start condition,
3. Read ICDRR every time RDRF is set. If the eighth clock pulse falls while RDRF is 1, SCL is
4. The last byte data is read by reading ICDRR.
(Master output)
(Master output)
ACKBT bit in ICIER and perform other initial settings. Set the MST and TRS bits in ICCRA
to select slave receive mode and wait until the slave address matches.
the slave address outputs the level specified by ACKBT in ICIER to SDA, at the rising of the
ninth clock pulse. At the same time, RDRF in ICSR is set to read ICDRR (dummy read).
(Since the read data shows the slave address and R/W, it is not used).
fixed to a low level until ICDRR is read. The change of the acknowledge (ACKBT) setting
before reading ICDRR to be returned to the master device is reflected in the next transmit
frame.
(Slave output)
(Slave output)
processing
ICDRS
ICDRR
RDRF
SDA
SDA
User
SCL
SCL
Slave Receive Operation
[2] Read ICDRR (dummy read)
Figure 17.11 Slave Receive Mode Operation Timing 1
A
9
Bit 7
1
Data 1
Bit 6
2
Bit 5
3
Bit 4
4
Bit 3
5
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Bit 2
6
Section 17 I
Bit 1
7
Bit 0
2
8
C Bus Interface 2 (IIC2)
[2] Read ICDRR
REJ09B0414-0200
A
9
Data 1
Bit 7
1
Data 2