R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 280

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 8 Bus Controller (BSC)
8.11.3
Figure 8.43 shows the timing for transition to the bus released state.
Rev. 2.00 Sep. 16, 2009 Page 250 of 1036
REJ09B0414-0200
[1] A low level of the BREQ signal is sampled at the rising edge of the Bφ signal.
[2] The bus control signals are driven high at the end of the external space access cycle. It takes two cycles or
[3] The BACK signal is driven low, releasing bus to the external bus master.
[4] The BREQ signal state sampling is continued in the external bus released state.
[5] A high level of the BREQ signal is sampled.
[6] The external bus released cycles are ended one cycle after the BREQ signal is driven high.
[7] When the external space is accessed by an internal bus master during external bus released while the BREQOE
[8] Normally the BREQO signal goes high at the rising edge of the BACK signal.
Bφ
Address bus
Data bus
CSn
AS
RD
LHWR, LLWR
BREQ
BACK
BREQO
more after the low level of the BREQ signal is sampled.
bit is set to 1, the BREQO signal goes low.
Transition Timing
Figure 8.43 Bus Released State Transition Timing
External space
access cycle
[1]
T
1
T
2
[2]
[3]
[4]
External bus released state
[7]
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
[5]
[8]
[6]
CPU cycle