R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 115

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.1
As table 5.1 indicates, exception handling is caused by a reset, a trace, an address error, an
interrupt, a trap instruction, and an illegal instruction (general illegal instruction or slot illegal
instruction). Exception handling is prioritized as shown in table 5.1. If two or more exceptions
occur simultaneously, they are accepted and processed in order of priority. Exception sources, the
stack structure, and operation of the CPU vary depending on the interrupt control mode. For
details on the interrupt control mode, see section 6, Interrupt Controller.
Table 5.1
Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not
Priority
High
Low
2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC
3. Trap instruction exception handling requests and sleep instruction exception handling
4. The external interrupt input pins usable in deep software standby mode are IRQ3 to
Exception Handling Types and Priority
Exception Type
Reset
Illegal instruction
Trace*
Address error
Interrupt
Sleep instruction
Trap instruction*
executed after execution of an RTE instruction.
instruction execution, or on completion of reset exception handling.
requests are accepted at all times in program execution state.
IRQ0 (IRQnA pins only) and NMI.
Exception Types and Priority
1
Section 5 Exception Handling
3
Exception Handling Start Timing
Exception handling starts at the timing of low-to-high transition on
the RES pin, watchdog timer overflow, or input of an external
interrupt signal*
state when the RES pin is low.
Exception handling starts when an undefined code is executed.
Exception handling starts after execution of the current instruction or
exception handling when the trace (T) bit in EXR has been set to 1,
After an address error has occurred, exception handling starts on
completion of instruction execution.
When an interrupt request has occurred, exception handling starts
after execution of the current instruction or exception handling.*
Exception handling starts by execution of a sleep instruction
(SLEEP) when the SSBY bit in SBYCR has been cleared to 0 and
the SLPIE bit in SBYCR has been set to 1.
Exception handling starts by execution of a trap instruction
(TRAPA).
4
in deep standby mode. The CPU enters the reset
Rev. 2.00 Sep. 16, 2009 Page 85 of 1036
Section 5 Exception Handling
REJ09B0414-0200
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