R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 302

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 9 DMA Controller (DMAC)
Rev. 2.00 Sep. 16, 2009 Page 272 of 1036
REJ09B0414-0200
Bit
30
29
28
27
26
25, 24
23
22 to 20 
Bit Name
DACKE
TENDE

DREQS
NRD

ACT
Initial
Value
0
0
0
0
0
All 0
0
All 0
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
Description
DACK Signal Output Enable
Enables/disables the DACK signal output in single
address mode. This bit is ignored in dual address mode.
0: Enables DACK signal output
1: Disables DACK signal output
TEND Signal Output Enable
Enables/disables the TEND signal output.
0: Enables TEND signal output
1: Disables TEND signal output
Reserved
Initial value should not be changed.
DREQ Select
Selects whether a low level or the falling edge of the
DREQ signal used in external request mode is detected.
When a block transfer is performed in external request
mode, clear this bit to 0.
0: Low level detection
1: Falling edge detection (the first transfer after a
Next Request Delay
Selects the accepting timing of the next transfer request.
0: Starts accepting the next transfer request after
1: Starts accepting the next transfer request one cycle
Reserved
These bits are always read as 0 and cannot be
modified.
Active State
Indicates the operating state for the channel.
0: Waiting for a transfer request or a transfer disabled
1: Active state
Reserved
These bits are always read as 0 and cannot be
modified.
transfer enabled is detected on a low level)
completion of the current transfer
after completion of the current transfer
state by clearing the DTE bit to 0