R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 417

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

11.1.4
ICR is an 8-bit readable/writable register that controls the port input buffers.
For bits in ICR set to 1, the input buffers of the corresponding pins are valid. For bits in ICR
cleared to 0, the input buffers of the corresponding pins are invalid and the input signals are fixed
high.
When the pin functions as an input for the peripheral modules, the corresponding bits should be
set to 1. The initial value should be written to a bit whose corresponding pin is not used as an input
or is used as an analog input/output pin.
If the bits in ICR have been cleared to 0, the pin state is not reflected to the peripheral modules.
When PORT is read, the pin status is always read regardless of the ICR value.
If ICR is modified, an internal edge may occur depending on the pin status. Accordingly, ICR
should be modified when the corresponding input pins are not used. For example, in IRQ input,
modify ICR while the corresponding interrupt is disabled, clear the IRQF flag in ISR of the
interrupt controller to 0, and then enable the corresponding interrupt. If an edge occurs after the
ICR setting, the edge should be cancelled.
The initial value of ICR is H'00.
Bit
Bit Name
Initial Value
R/W
Note:
The lower six bits are valid and the upper two bits are reserved for port 6 registers.
The lower five bits are valid and the upper three bits are reserved for port F registers.
Input Buffer Control Register (PnICR) (n = 1 to 6, A, D to F, H, and I)
Pn7ICR
R/W
7
0
Pn6ICR
R/W
6
0
Pn5ICR
R/W
5
0
Pn4ICR
R/W
4
0
Pn3ICR
R/W
3
0
Rev. 2.00 Sep. 16, 2009 Page 387 of 1036
Pn2ICR
R/W
2
0
Pn1ICR
R/W
Section 11 I/O Ports
1
0
REJ09B0414-0200
Pn0ICR
R/W
0
0