R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 755

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

18.4.2
In scan mode, A/D conversion is to be performed sequentially on the analog inputs of the specified
channels up to four or eight* channels. Two types of scan mode are provided, that is, continuous
scan mode where A/D conversion is repeatedly performed and one-cycle scan mode where A/D
conversion is performed for the specified channels for one cycle.
(1)
1. When the ADST bit in ADCSR is set to 1 by software, TPU, TMR, or an external trigger
2. When A/D conversion for each channel is completed, the A/D conversion result is sequentially
3. When A/D conversion of all selected channels is completed, the ADF bit in ADCSR is set to 1.
4. The ADST bit is not cleared automatically, and steps 2 to 3 are repeated as long as the ADST
input, A/D conversion starts on the first channel in the specified channel group. Consecutive
A/D conversion on a maximum of four channels (SCANE and SCANS = B'10) or on a
maximum of eight channels (SCANE and SCANS = B'11) can be selected. When consecutive
A/D conversion is performed on four channels, A/D conversion starts on AN0 when CH3 and
CH2 = B'00, whereas starts on AN4 when CH3 and CH2 = B'01. When consecutive A/D
conversion is performed on eight channels, A/D conversion starts on AN0 when CH3 = B'0.
transferred to the corresponding ADDR of each channel.
If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. A/D conversion of
the first channel in the group starts again.
bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops and the A/D
converter enters wait state. If the ADST bit is later set to 1, A/D conversion starts again from
the first channel in the group.
Continuous Scan Mode
Scan Mode
Rev. 2.00 Sep. 16, 2009 Page 725 of 1036
Section 18 A/D Converter
REJ09B0414-0200