R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 286

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 8 Bus Controller (BSC)
• During transfer information read
• During the first data transfer
• During transfer information write back
The DTC releases the bus when the consecutive transfer cycles completed.
(3)
The DMAC sends the internal bus arbiter a request for the bus when an activation request is
generated. When the DMAC accesses an external bus space, the DMAC first takes control of the
bus from the internal bus arbiter and then requests a bus to the external bus arbiter.
After the DMAC takes control of the bus, it may continue the transfer processing cycles or release
the bus at the end of every bus cycle depending on the conditions.
The DMAC continues transfers without releasing the bus in the following case:
• Between the read cycle in the dual-address mode and the write cycle corresponding to the read
If no bus master of a higher priority than the DMAC requests the bus and the IBCCS bit in BCR2
is cleared to 0, the DMAC continues transfers without releasing the bus in the following cases:
• During 1-block transfers in the block transfer mode
• During transfers in the burst mode
In other cases, the DMAC transfers the bus at the end of the bus cycle.
(4)
When the BREQ pin goes low and an external bus release request is issued while the BRLE bit in
BCR1 is set to 1 with the corresponding ICR bit set to 1, a bus request is sent to the bus arbiter.
External bus release can be performed on completion of an external bus cycle.
Rev. 2.00 Sep. 16, 2009 Page 256 of 1036
REJ09B0414-0200
cycle
DMAC
External Bus Release