R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 783

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

19.4.1
When the ∆Σ A/D converter is to be used, register settings should be made in accord with the
procedure for activation given below.
Figure 19.2 shows the procedure for activating the ∆Σ A/D converter.
Set the TRGS1 and TRGS0 bits in DSADCSR
(ADIE, SCANE, CH5 to CH0, CKS, GAIN)
Clear the MSTPC14 bit in MSTPCRC to 0
Set the ACK2 to ACK0 bits in DSADMR
Set ADST = 1 to start A/D conversion
Set the bits in DSADCSR/DSADCR
Set the BIASE bit in DSADMR to 1
Set the DSE bit in DSADCR to 1
Procedure for Activating the ∆Σ A/D Converter
Figure 19.2 Procedure for Activating the ∆Σ A/D Converter
Start
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
Starts the biasing circuit.
To ensure stabilization of the circuit, a period of waiting is
necessary after the biasing circuit has started up and by the
time step [7] is executed. See section 19.6, Usage Notes, for
details. BIASE should be set while the ∆Σ A/D converter is in
the module stop state.
Sets a frequency-divided clock signal for the ∆Σ A/D
converter. When changing the clock-division setting, put the
∆Σ A/D converter in the module stop state.
Releases the ∆Σ A/D converter from the module stop state.
On release, supply of the Aφ clock and the Pφ clock
connected to the ∆Σ A/D converter start.
Starts the ∆Σ modulator.
The analog circuit starts to operate, consuming a certain
amount of power. The ∆Σ A/D converter enters the idle state.
Sets the operating mode of the ∆Σ A/D converter, selects
channels, etc.
Sets the trigger input for starting A/D conversion.
Leave the bits at the initial value if A/D conversion is to be
started by software.
A/D conversion starts when ADST is set to 1 by software or
by input of the trigger set in step [6].
Rev. 2.00 Sep. 16, 2009 Page 753 of 1036
Section 19 ∆Σ A/D Converter
REJ09B0414-0200