R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 510

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 12 16-Bit Timer Pulse Unit (TPU)
12.4
12.4.1
Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of
free-running operation, periodic counting, and external event counting.
Each TGR can be used as an input capture register or output compare register.
(1)
When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for the corresponding
channel starts counting. TCNT can operate as a free-running counter, periodic counter, and so on.
(a)
Figure 12.2 shows an example of the count operation setting procedure.
Rev. 2.00 Sep. 16, 2009 Page 480 of 1036
REJ09B0414-0200
Select output compare register
Select counter clearing source
Counter Operation
Example of count operation setting procedure
Select counter clock
Operation selection
<Periodic counter>
Periodic counter
Operation
Basic Functions
Start count
Set period
Figure 12.2 Example of Counter Operation Setting Procedure
[1]
[2]
[3]
[4]
[5]
<Free-running counter>
Free-running counter
Start count
[5]
[1]
[2]
[3]
[4]
[5]
Select the counter clock with bits TPSC2
to TPSC0 in TCR. At the same time,
select the input clock edge with bits
CKEG1 and CKEG0 in TCR.
For periodic counter operation, select the
TGR to be used as the TCNT clearing
source with bits CCLR2 to CCLR0 in
TCR.
Designate the TGR selected in [2] as an
output compare register by means of
TIOR.
Set the periodic counter cycle in the TGR
selected in [2].
Set the CST bit in TSTR to 1 to start the
counter operation.