R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 282

MCU 24KB FLASH 384K 144-LQFP

R5F61662N50FPV

Manufacturer Part Number
R5F61662N50FPV
Description
MCU 24KB FLASH 384K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61662N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61662N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 8 Bus Controller (BSC)
8.13
8.13.1
This LSI has a write data buffer function for the external data bus. Using the write data buffer
function enables internal accesses in parallel with external writes or DMAC single address
transfers. The write data buffer function is made available by setting the WDBE bit to 1 in BCR1.
Figure 8.44 shows an example of the timing when the write data buffer function is used. When this
function is used, if an external address space write or a DMAC single address transfer continues
for two cycles or longer, and there is an internal access next, an external write only is executed in
the first two cycles. However, from the next cycle onward, internal accesses (on-chip memory or
internal I/O register read/write) and the external address space write rather than waiting until it
ends are executed in parallel.
Rev. 2.00 Sep. 16, 2009 Page 252 of 1036
REJ09B0414-0200
External
space
write
Figure 8.44 Example of Timing when Write Data Buffer Function is Used
Write Data Buffer Function
Write Data Buffer Function for External Data Bus
Internal
address bus
A23 to A0
CSn
LHWR, LLWR
D15 to D0
T
1
External write cycle
On-chip
memory 1
On-chip memory read
External address
T
2
memory 2
On-chip
Peripheral module address
Peripheral module read
T
3

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