R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 777

MCU 24KB FLASH 384K 144-LQFP

R5F61662N50FPV

Manufacturer Part Number
R5F61662N50FPV
Description
MCU 24KB FLASH 384K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61662N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61662N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Bit
15
14
13
Bit Name
ADF
ADIE
ADST
Initial
Value
0
0
0
R/W
R/(W)*
R/W
R/W
1
A/D Conversion End Flag
Indicates whether A/D conversion has ended.
[Setting condition]
[Clearing conditions]
A/D Conversion Interrupt Enable
Setting this bit to 1 enables generation of DSADI interrupt
requests in accord with the ADF bit.
A/D Conversion Start
Controls starting and stopping of A/D conversion.
Clearing this bit to 0 stops A/D conversion, placing the
converter in the wait sate. Setting this bit to 1 starts A/D
conversion.
In single mode, ADST is automatically cleared at the end
of A/D conversion on the selected channels. In scan
mode, ADST must be cleared by software because it is not
cleared automatically.
[Setting conditions]
[Clearing conditions]
Description
A/D conversion on all of the selected channels has
ended.
Writing 0 to ADF after reading it as 1
Activation of the DMAC by the DSADI interrupt and
transfer of data in DSADDRn.
Writing 1 to ADST by software
Input of an A/D conversion trigger signal while starting
of A/D conversion by a trigger is enabled (TRGS1,
TRGS0 ≠ B'00)
Writing 0 to ADST by software
End of A/D conversion on all selected channels while
SCANE = 0
Rev. 2.00 Sep. 16, 2009 Page 747 of 1036
Section 19 ∆Σ A/D Converter
REJ09B0414-0200

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