R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 782

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 19 ∆Σ A/D Converter
Table 19.3 Analog Levels for Offset Cancellation and Register Settings (Calculated
19.4
The ∆Σ A/D converter uses a ∆Σ modulator to convert analog input voltages within the range
specified by the voltages on the AVrefT and AVrefB pins to digital values with 16-bit resolution.
The ∆Σ A/D converter is made up of three parts: an analog block built around a ∆Σ modulator, a
digital filter, and a control circuit.
In the analog block, the ∆Σ modulator amplifies the input signals (eight-fold when the GAIN1 and
GAIN0 bits in DSADCR is set to B'11) and converts them. During this process, the DC offsets of
the signals input from the single-ended input signal pins (ANDS0, ANDS1, ANDS2, ANDS3) are
cancelled if offset values have been set in the DSADOF0 to DSADOF3 registers. Differential
input voltages on the differential input pins (ANDS4P, ANDS4N and ANDS5P, ANDS5N) can
also be converted.
The voltage of a selected analog input signal is sampled at the Aφ/8 clock frequency
(oversampling frequency) and converted to a series of digital values by the second-order ∆Σ
modulator. The result of conversion is passed through a decimation filter (digital filter) and stored
in the corresponding ∆Σ A/D data register as a 16-bit signed binary number (two's complement).
The ∆Σ A/D converter operates in either single mode or scan mode. Multiple channels are
specified by selecting multiple A/D conversion channel-selection bits.
Rev. 2.00 Sep. 16, 2009 Page 752 of 1036
REJ09B0414-0200
DSADOF[9:0]
H'000
H'001
H'002
H'100
H'200
H'3FF
Operation
Examples)
Analog Level for Offset Cancellation
0/1024 × ( AVrefT – AVrefB )
1/1024 × ( AVrefT – AVrefB )
2/1024 × ( AVrefT – AVrefB )
256/1024 × ( AVrefT – AVrefB )
512/1024 × ( AVrefT – AVrefB )
1023/1024 × ( AVrefT – AVrefB )
Value Calculated for
AVrefT – AVrefB = 3.0 V
AVrefB = 0 V
0.0000
0.0029
0.0059
0.7500
1.5000
2.9971