R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 798

MCU 24KB FLASH 384K 144-LQFP

R5F61662N50FPV

Manufacturer Part Number
R5F61662N50FPV
Description
MCU 24KB FLASH 384K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61662N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61662N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 19 ∆Σ A/D Converter
19.6.3
If the LSI enters software standby mode with A/D conversion enabled, the ∆Σ A/D converter is
initialized and placed in an idle state. The ∆Σ A/D data registers (DSADDRn), which hold the
results of conversion, are also initialized. The analog power supply current is the current that flows
through the biasing circuit. If the analog power supply current in software standby mode must be
reduced, clear the BIASE bit in DSDMR to 0 to stop the biasing circuit before initiating software
standby mode.
19.6.4
To avoid malfunctions during A/D conversion, do not change the settings of the ∆Σ A/D converter
registers while the ADST bit in DSADCSR is set to 1. Always write to the registers with the
ADST bit cleared to 0. The exceptions are clearing of the ADST bit and clearing of the ADF bit
after reading a 1 from it.
When the TRGS1 and TRGS0 bits in DSADCSR are set to a value other than B'00, the ADST bit
may be set automatically by the trigger signal. Accordingly, before setting registers of the ∆Σ A/D
converter, set the TRGS1 and TRGS0 bits to B'00 or take measures to ensure that no trigger signal
will be input.
19.6.5
Use the ∆Σ A/D converter with the DSE bit in DSADCR set to 1.
Rev. 2.00 Sep. 16, 2009 Page 768 of 1036
REJ09B0414-0200
State of the ∆Σ A/D Converter in Software Standby Mode
Changing the Settings of ∆Σ A/D Converter Registers
DSE Bit

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