R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 787

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3. After A/D conversion for channel n, A/D conversion for the next channel is started. Steps 2
4. When A/D conversion for all of the selected channels has been completed, the ADF bit in
5. The ADST bit remains set to 1 during A/D conversion and is automatically cleared on
6. If the ADST bit is cleared to 0 during A/D conversion, the conversion is stopped and the ∆Σ
Channel 0 (ANDS0)
Channel 1 (ANDS1)
Channel 3 (ANDS3)
Channel 2 (ANDS2)
Figure 19.4 Example of ∆Σ A/D Converter Operation (Single Mode for Multiple Channels:
State of operation
State of operation
State of operation
State of operation
and 3 are repeated until A/D conversion for all of the selected channels has been completed.
DSADCSR is set to 1. If the setting of the ADIE bit in DSADCSR is 1 at this time, a DSADI
interrupt request is also generated.
completion of A/D conversion. When the ADST bit is subsequently set to 1, A/D conversion
for the selected channels again proceeds from channel 0.
A/D converter enters the idle state.
DSADDR0
DSADDR1
DSADDR2
DSADDR3
ADIE
ADST
ADF
Note: *
indicates execution of a software instruction.
Idle
Idle
Idle
Idle
Start A/D
conversion
A/D
Set*
Set*
conversion
1
Channels 0 to 2)
A/D
Idle
conversion
A/D
conversion result
2
A/D
Idle
conversion
A/D
1
conversion result
Rev. 2.00 Sep. 16, 2009 Page 757 of 1036
3
Idle
A/D
Section 19 ∆Σ A/D Converter
conversion result
2
Clear*
REJ09B0414-0200
3