R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 148

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 6 Interrupt Controller
6.3.6
ISR is an IRQ15 to IRQ0 interrupt request register. However, the bits of this register cannot set the
IRQ interrupt request flags, IRQnF (n = 3 to 0), to exit from deep software standby mode. For
details, see section 24.2.7, Deep Standby Interrupt Flag Register (DPSIFR).
Notes: 1. Only 0 can be written, to clear the flag.
Rev. 2.00 Sep. 16, 2009 Page 118 of 1036
REJ09B0414-0200
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Note: *
2. The bits of this register cannot set the IRQ interrupt request flags, IRQnF (n = 3 to 0), to
IRQ Status Register (ISR)
Only 0 can be written, to clear the flag. The bit manipulation instructions or memory operation instructions should
be used to clear the flag.
Bit Name
IRQ15F
IRQ14F
IRQ13F
IRQ12F
IRQ11F
IRQ10F
IRQ9F
IRQ8F
IRQ7F
IRQ6F
IRQ5F
IRQ4F
IRQ3F*
IRQ2F*
IRQ1F*
IRQ0F*
exit from deep software standby mode. For details, see section 24.2.7, Deep Standby
Interrupt Flag Register (DPSIFR).
IRQ15F
R/(W)*
R/(W)*
IRQ7F
15
0
7
0
2
2
2
2
Initial
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IRQ14F
R/(W)*
R/(W)*
IRQ6F
14
0
6
0
R/W
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
IRQ13F
R/(W)*
R/(W)*
IRQ5F
13
0
5
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Description
[Setting condition]
•
[Clearing conditions]
•
•
•
•
IRQ12F
R/(W)*
R/(W)*
IRQ4F
When the interrupt selected by ISCR occurs
Writing 0 after reading IRQnF = 1 (n = 11 to 0)
When interrupt exception handling is executed while
low-level sensing is selected and IRQn input is high
When IRQn interrupt exception handling is executed
while falling-, rising-, or both-edge sensing is
selected
When the DTC is activated by an IRQn interrupt,
and the DISEL bit in MRB of the DTC is cleared to 0
(n = 15 to 0)
12
0
4
0
IRQ11F
R/(W)*
R/(W)*
IRQ3F
11
0
3
0
IRQ10F
R/(W)*
R/(W)*
IRQ2F
10
0
2
0
R/(W)*
R/(W)*
IRQ9F
IRQ1F
9
0
1
0
R/(W)*
R/(W)*
IRQ8F
IRQ0F
8
0
0
0