R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 17

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9.4
9.5
9.6
9.7
9.8
9.9
Section 10 Data Transfer Controller (DTC) ......................................................339
10.1
10.2
10.3
10.4
9.3.7
9.3.8
Transfer Modes ................................................................................................................. 285
Operations......................................................................................................................... 286
9.5.1
9.5.2
9.5.3
9.5.4
9.5.5
9.5.6
9.5.7
9.5.8
9.5.9
9.5.10
9.5.11
DMA Transfer End ........................................................................................................... 328
Relationship among DMAC and Other Bus Masters ........................................................ 331
9.7.1
9.7.2
Interrupt Sources............................................................................................................... 333
Usage Notes ...................................................................................................................... 336
9.9.1
9.9.2
9.9.3
9.9.4
Features............................................................................................................................. 339
Register Descriptions........................................................................................................ 341
10.2.1
10.2.2
10.2.3
10.2.4
10.2.5
10.2.6
10.2.7
10.2.8
10.2.9
Activation Sources............................................................................................................ 349
Location of Transfer Information and DTC Vector Table ................................................ 350
DMA Address Control Register (DACR) ......................................................... 278
DMA Module Request Select Register (DMRSR) ........................................... 284
Address Modes ................................................................................................. 286
Transfer Modes ................................................................................................. 290
Activation Sources............................................................................................ 295
Bus Access Modes ............................................................................................ 297
Extended Repeat Area Function ....................................................................... 299
Address Update Function using Offset ............................................................. 301
Register during DMA Transfer ......................................................................... 306
Priority of Channels .......................................................................................... 311
DMA Basic Bus Cycle...................................................................................... 313
Bus Cycles in Dual Address Mode ................................................................... 314
Bus Cycles in Single Address Mode................................................................. 323
CPU Priority Control Function Over DMAC ................................................... 331
Bus Arbitration among DMAC and Other Bus Masters ................................... 332
DMAC Register Access During Operation....................................................... 336
Settings of Module Stop Function .................................................................... 336
Activation by DREQ Falling Edge ................................................................... 336
Acceptation of Activation Source ..................................................................... 337
DTC Mode Register A (MRA) ......................................................................... 342
DTC Mode Register B (MRB).......................................................................... 343
DTC Source Address Register (SAR)............................................................... 345
DTC Destination Address Register (DAR)....................................................... 345
DTC Transfer Count Register A (CRA) ........................................................... 346
DTC Transfer Count Register B (CRB)............................................................ 346
DTC enable registers A to H (DTCERA to DTCERH) .................................... 347
DTC Control Register (DTCCR) ...................................................................... 348
DTC Vector Base Register (DTCVBR)............................................................ 349
Rev. 2.00 Sep. 16, 2009 Page xv of xxviii