R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 18

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10.5
10.6
10.7
10.8
10.9
Section 11 I/O Ports........................................................................................... 377
11.1
11.2
Rev. 2.00 Sep. 16, 2009 Page xvi of xxviii
Operation .......................................................................................................................... 355
10.5.1
10.5.2
10.5.3
10.5.4
10.5.5
10.5.6
10.5.7
10.5.8
10.5.9
10.5.10 DTC Bus Release Timing ................................................................................. 368
10.5.11 DTC Priority Level Control to the CPU ........................................................... 368
DTC Activation by Interrupt............................................................................................. 369
Examples of Use of the DTC............................................................................................ 370
10.7.1
10.7.2
10.7.3
Interrupt Sources............................................................................................................... 373
Usage Notes ...................................................................................................................... 373
10.9.1
10.9.2
10.9.3
10.9.4
10.9.5
10.9.6
10.9.7
10.9.8
10.9.9
Register Descriptions........................................................................................................ 384
11.1.1
11.1.2
11.1.3
11.1.4
11.1.5
11.1.6
Output Buffer Control....................................................................................................... 391
11.2.1
Transfer Information Start Address, Source Address, and
Destination Address .......................................................................................... 374
Bus Cycle Division ........................................................................................... 357
Transfer Information Read Skip Function ........................................................ 359
Transfer Information Writeback Skip Function................................................ 360
Normal Transfer Mode ..................................................................................... 360
Repeat Transfer Mode ...................................................................................... 361
Block Transfer Mode ........................................................................................ 363
Chain Transfer .................................................................................................. 364
Operation Timing.............................................................................................. 365
Number of DTC Execution Cycles ................................................................... 367
Normal Transfer Mode ..................................................................................... 370
Chain Transfer .................................................................................................. 370
Chain Transfer when Counter = 0..................................................................... 371
Module Stop Function Setting .......................................................................... 373
On-Chip RAM .................................................................................................. 373
DMAC Transfer End Interrupt.......................................................................... 373
DTCE Bit Setting.............................................................................................. 373
Chain Transfer .................................................................................................. 374
Transfer Information Modification ................................................................... 374
Endian Format .................................................................................................. 374
Points for Caution when Overwriting DTCER ................................................. 375
Data Direction Register (PnDDR) (n = 1 to 3, 6, A, D to F, H, and I).............. 385
Data Register (PnDR) (n = 1 to 3, 6, A, D to F, H, and I) ................................ 386
Port Register (PORTn) (n = 1 to 6, A, D to F, H, and I)................................... 386
Input Buffer Control Register (PnICR) (n = 1 to 6, A, D to F, H, and I).......... 387
Pull-Up MOS Control Register (PnPCR) (n = D to F, H, and I) ...................... 388
Open-Drain Control Register (PnODR) (n = 2 and F)...................................... 390
Port 1................................................................................................................. 391