R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 788

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 19 ∆Σ A/D Converter
19.4.4
In scan mode, A/D conversion is executed continuously for the specified analog input channels as
follows. A/D conversion for up to six analog input channels can be specified by setting the CH0 to
CH5 bits in DSADCSR to 1, indicating the required channels.
1. A/D conversion for the selected channels is started by a software instruction setting the ADST
2. When A/D conversion is completed for channel n, the result is transferred to the corresponding
3. When A/D conversion for all of the selected channels has been completed, the ADF bit in
4. The ∆Σ A/D converter starts another round of A/D conversion in order of precedence from
5. If the ADST bit is cleared to 0 during A/D conversion, the conversion is stopped and the ∆Σ
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bit in DSADCSR to 1 or input of the trigger signal selected by the TRGS1 and TRGS0 bits in
DSADCSR. When multiple channels have been selected, execution of A/D conversion is in
order of rising channel number, so the order of precedence starts from channel 0.
∆Σ A/D data register (DSADDRn, n = 0 to 5).
DSADCSR is set to 1. If the setting of the ADIE bit in DSADCSR is 1 at this time, a DSADI
interrupt request is also generated.
channel 0. The ADST bit is not cleared automatically, and steps 2 to 4 are repeated as long as
ADST = 1.
A/D converter enters the idle state. When the ADST bit is subsequently set to 1, A/D
conversion for the selected channels again proceeds from channel 0.
Scan Mode