R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 639

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit Functions in Smart Card Interface Mode (When SMIF in SCMR = 1):
Bit
7
6
5
4
3
2
Bit Name
GM
BLK
PE
O/E
BCP1
BCP0
Initial
Value
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
GSM Mode
Setting this bit to 1 allows GSM mode operation. In
GSM mode, the TEND set timing is put forward to 11.0
etu from the start and the clock output control function
is appended. For details, see sections 16.7.6, Data
Transmission (Except in Block Transfer Mode) and
16.7.8, Clock Output Control.
Setting this bit to 1 allows block transfer mode
operation. For details, see section 16.7.3, Block
Transfer Mode.
Parity Enable (valid only in asynchronous mode)
When this bit is set to 1, the parity bit is added to
transmit data before transmission, and the parity bit is
checked in reception. Set this bit to 1 in smart card
interface mode.
Parity Mode (valid only when the PE bit is 1 in
asynchronous mode)
0: Selects even parity
1: Selects odd parity
For details on the usage of this bit in smart card
interface mode, see section 16.7.2, Data Format
(Except in Block Transfer Mode).
Basic Clock Pulse 1,0
These bits select the number of basic clock cycles in a
1-bit data transfer time in smart card interface mode.
00: 32 clock cycles (S = 32)
01: 64 clock cycles (S = 64)
10: 372 clock cycles (S = 372)
11: 256 clock cycles (S = 256)
For details, see section 16.7.4, Receive Data Sampling
Timing and Reception Margin. S is described in section
16.3.9, Bit Rate Register (BRR).
Section 16 Serial Communication Interface (SCI)
Rev. 2.00 Sep. 16, 2009 Page 609 of 1036
REJ09B0414-0200