R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 954

MCU 24KB FLASH 384K 144-LQFP

R5F61662N50FPV

Manufacturer Part Number
R5F61662N50FPV
Description
MCU 24KB FLASH 384K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61662N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61662N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 24 Power-Down Modes
24.11
Output of the Bφ clock can be controlled by the PSTOP1 bit in SCKCR, and DDR for the
corresponding PA7 pin.
Clearing the PSTOP1 bit to 0 enables the Bφ clock output on the PA7 pin. When bit PSTOP1 is
set to 1, the Bφ clock output stops at the end of the bus cycle, and the Bφ clock output goes high.
When DDR for the PA7 pin is cleared to 0, the Bφ clock output is disabled and the pin becomes an
input port. Tables 24.4 shows the states of the Bφ pin in each processing state.
Table 24.4 φ Pin (PA7) State in Each Processing State
[Legend]
x = Don't care
Rev. 2.00 Sep. 16, 2009 Page 924 of 1036
REJ09B0414-0200
DDR
0
1
1
Setting Value
Register
PSTOP1
x
0
1
Bφ Clock Output Control
Normal
Operating
Mode
Hi-Z
Bφ output
High
Sleep
Mode
Hi-Z
Bφ output
High
All-Module-
Clock-Stop
Mode
Hi-Z
Bφ output
High
OPE = 0
Hi-Z
High
High
Standby Mode
Software
OPE = 1
Hi-Z
High
High
IOKEEP = 0 IOKEEP = 1
Hi-Z
High
High
Deep Software
Standby Mode
Hi-Z
High
High
Hardware
Standby
Mode
Hi-Z
Hi-Z
Hi-Z

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