R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 25

MCU 24KB FLASH 384K 144-LQFP

R5F61662N50FPV

Manufacturer Part Number
R5F61662N50FPV
Description
MCU 24KB FLASH 384K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61662N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61662N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
18.5
18.6
18.7
Section 19 ∆Σ A/D Converter..............................................................................741
19.1
19.2
19.3
19.4
19.5
19.6
18.4.1
18.4.2
18.4.3
18.4.4
Interrupt Source ................................................................................................................ 730
A/D Conversion Accuracy Definitions ............................................................................. 730
Usage Notes ...................................................................................................................... 732
18.7.1
18.7.2
18.7.3
18.7.4
18.7.5
18.7.6
18.7.7
18.7.8
18.7.9
Features............................................................................................................................. 741
Input/Output Pins.............................................................................................................. 743
Register Descriptions........................................................................................................ 744
19.3.1
19.3.2
19.3.3
19.3.4
19.3.5
Operation .......................................................................................................................... 752
19.4.1
19.4.2
19.4.3
19.4.4
19.4.5
19.4.6
19.4.7
Interrupt Source ................................................................................................................ 766
Usage Notes ...................................................................................................................... 767
19.6.1
19.6.2
19.6.3
19.6.4
Single Mode...................................................................................................... 723
Scan Mode ........................................................................................................ 725
Input Sampling and A/D Conversion Time ...................................................... 727
External Trigger Input Timing.......................................................................... 729
Module Stop Function Setting .......................................................................... 732
A/D Input Hold Function in Software Standby Mode ...................................... 732
Notes on A/D Conversion Start by an External Trigger ................................... 732
Notes on Stopping the A/D Converter .............................................................. 734
Permissible Signal Source Impedance .............................................................. 737
Influences on Absolute Accuracy ..................................................................... 737
Setting Range of Analog Power Supply and Other Pins ................................... 738
Notes on Board Design ..................................................................................... 738
Notes on Countermeasure against Noise........................................................... 738
∆Σ A/D Mode Register (DSADMR)................................................................. 745
∆Σ A/D Data Registers 0 to 5 (DSADDR0 to DSADDR5) .............................. 746
∆Σ A/D Control/Status Register (DSADCSR).................................................. 746
∆Σ A/D Control Register (DSADCR)............................................................... 749
∆Σ A/D Offset Cancel DAC Inputs 0 to 3 (DSADOF0 to DSADOF3) ............ 751
Procedure for Activating the ∆Σ A/D Converter .............................................. 753
Selecting Analog Input Channels...................................................................... 754
Single Mode...................................................................................................... 755
Scan Mode ........................................................................................................ 758
Flow of ∆Σ A/D Conversion Operation ............................................................ 760
Analog Input Sampling and A/D Conversion Time.......................................... 762
External Trigger Input Timing.......................................................................... 765
Module Stop Function Setting .......................................................................... 767
Settings for the Biasing Circuit......................................................................... 767
State of the ∆Σ A/D Converter in Software Standby Mode .............................. 768
Changing the Settings of ∆Σ A/D Converter Registers..................................... 768
Rev. 2.00 Sep. 16, 2009 Page xxiii of xxviii

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