R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 278

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 8 Bus Controller (BSC)
8.11
This LSI can release the external bus in response to a bus request from an external device. In the
external bus released state, internal bus masters continue to operate as long as there is no external
access.
In addition, in the external bus released state, the BREQO signal can be driven low to output a bus
request externally.
8.11.1
In external extended mode, when the BRLE bit in BCR1 is set to 1 and the ICR bits for the
corresponding pin are set to 1, the bus can be released to the external. Driving the BREQ pin low
issues an external bus request to this LSI. When the BREQ pin is sampled, at the prescribed
timing, the BACK pin is driven low, and the address bus, data bus, and bus control signals are
placed in the high-impedance state, establishing the external bus released state. For details on
DDR and ICR, see section 11, I/O Ports.
In the external bus released state, the CPU, DTC, and DMAC can access the internal space using
the internal bus. When the CPU, DTC, or DMAC attempts to access the external address space, it
temporarily defers initiation of the bus cycle, and waits for the bus request from the external bus
master to be canceled.
If the BREQOE bit in BCR1 is set to 1, the BREQO pin can be driven low when any of the
following requests are issued, to request cancellation of the bus request externally.
• When the CPU, DTC, or DMAC attempts to access the external address space
• When a SLEEP instruction is executed to place the chip in software standby mode or all-
• When SCKCR is written to for setting the clock frequency
If an external bus release request and external access occur simultaneously, the priority is as
follows:
Rev. 2.00 Sep. 16, 2009 Page 248 of 1036
REJ09B0414-0200
module-clock-stop mode
(High) External bus release > External access by CPU, DTC, or DMAC (Low)
Bus Release
Operation