IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 102

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Configuration Registers
Configuration
Registers
3–28
PCI Compiler User Guide
In master mode, the pci_mt64 and pci_mt32 functions can initiate
transactions of standard memory read/write, cache memory read/write,
I/O read/write, and configuration read/write commands. Per the PCI
specification, the master must keep track of the number of words that are
transferred and can only end the transaction at cache line boundaries
during memory read line (MRL) and memory write-and-invalidate
(MWI) commands. It is the responsibility of the local-side interface to
ensure that this requirement is not violated. Additionally, it is the
responsibility of the local-side interface to ensure that proper address and
byte enable combinations are used during I/O read/write cycles.
Each logical PCI bus device includes a block of 64 configuration DWORDs
reserved for the implementation of its configuration registers. The format
of the first 16 DWORDs is defined by the PCI Special Interest Group
(PCI SIG) PCI Local Bus Specification, Revision 3.0 and the Compliance
Checklist, Revision 3.0. These specifications define two header formats,
type one and type zero. Header type one is used for PCI-to-PCI bridges;
header type zero is used for all other devices, including the Altera PCI
MegaCore functions.
PCI Compiler Version 10.1
Altera Corporation
January 2011