IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 99

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
lm_rdyn
lm_adr_ackn
lm_ackn
lm_dxfrn
lm_tsr[9..0]
Table 3–9. PCI Master Signals Interfacing to the Local Side (Part 2 of 2)
Name
Output
Output
Output
Output
Input
Type
Polarity
Low
Low
Low
Low
–
PCI Compiler Version 10.1
Local master ready. The local side asserts the
indicate a valid data input during a master write, or ready to accept
data during a master read. During a master write, the
signal de-assertion suspends the current transfer (i.e., wait state is
inserted by the local side). During a master read, an inactive
lm_rdyn
states on the PCI bus. The only time
inserts wait states during a burst is when the
inserts wait states on the local side.
The
is transferred on the local side.
Local master address acknowledge.
assert the
the requested master transaction. During the same clock cycle
when
the transaction address on the
transaction command on the
Local master acknowledge.
lm_ackn
or ready to accept data during a master write. During a master
write, an inactive
pci_mt32
off the bursting operation. During a master read operation, the
lm_ackn
wait state is inserted by the PCI target). During a burst when the
PCI bus target inserts wait states, the
inactive.
Local master data transfer. During a master transaction,
pci_mt64
on the local side is successful.
Local master transaction status register bus. These signals inform
the local interface of the transaction’s progress. Refer to
for a detailed description of the bits in this bus.
lm_rdyn
lm_adr_ackn
lm_adr_ackn
signal to indicate valid data output during a master read,
signal de-assertion suspends the current transfer (i.e., a
signal directs
and
is not ready to accept data, and local logic should hold
signal is sampled one clock cycle before actual data
pci_mt32
lm_ackn
is asserted low, the local side must provide
pci_mt64
Description
signal to the local side to acknowledge
pci_mt64
signal indicates that
assert this signal when a data transfer
l_cmdi[3..0]
l_adi[31..0]
pci_mt64
or
pci_mt64
lm_ackn
pci_mt32
and
Functional Description
pci_mt32
lm_rdyn
lm_rdyn
bus.
pci_mt64
or
signal goes
bus and the
or
to insert wait
pci_mt32
pci_mt32
lm_rdyn
Table 3–10
signal
assert the
signal to
and
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