IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 213

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
Table 4–1
the tb_src directory. For more information on these files, refer to
“Testbench Specifications” on page
Note to
(1)
mstr_tranx
mstr_pkg
trgt_tranx
trgt_tranx_mem_init.dat This file is the memory initialization file for the target
monitor
clk_gen
arbiter
pull_up
altera_tb
Table 4–1. Files Contained in the tb_src Directory
All files are provided in both VHDL and Verilog HDL.
Table
File(1)
gives a description of the PCI testbench source files provided in
PCI Compiler Version 10.1
4–1:
The master transactor defines the procedures
(VHDL) or tasks (Verilog HDL) needed to initiate PCI
transactions in the testbench.
The master package consists descriptions of
procedures (VHDL) or tasks (Verilog HDL) of the
master transactor (mstr_tranx) commands.
The target transactor simulates the target behavior in
the testbench. It serves to respond to PCI
transactions.
transactor.
This module monitors the PCI transactions on the
bus and reports the results.
This module generates 33-or 66-MHz clock for the
PCI agents.
This module contains PCI bus arbiter.
This module is used to provide weak pull-up on the
tri-stated signals.
This is a sample top-level file that instantiates the
testbench modules and the IP functional simulation
model of the PCI MegaCore function. You can use
this sample top-level file in your application design by
replacing the
testbench file with the top level of your application
design. Refer to
more information.
4–6.
top_local
“Simulation Flow” on page 4–20
Description
PCI Compiler User Guide
instance from the
Testbench
for
4–3