IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 129

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Figure 3–9. Burst Memory Read Target Transaction with PCI Master Wait State
Note to
(1)
Altera Corporation
January 2011
(1) l_adi[63..32]
(1) ad[63..32]
(1) cben[7..4]
l_adro[31..0]
l_cmdo[3..0]
lt_tsr[11..0]
l_adi[31..0]
This signal is not applicable to the pci_mt32 or pci_t32 MegaCore functions.
(1) req64n
(1) ack64n
cben[3..0]
(1) par64
lt_framen
ad[31..0]
devseln
lt_dxfrn
lt_ackn
framen
lt_rdyn
stopn
trdyn
Figure
irdyn
par
clk
1
3–9:
2
000
Adr
6
3
Figure 3–9
master inserting a wait state. The PCI bus master inserts a wait state by
deasserting irdyn in clock cycle 8. The effect of this wait state on the local
side is shown in clock cycle 9 is that the PCI MegaCore function deasserts
lt_ackn, and as a result lt_dxfrn is also deasserted. This situation
prevents further data from being transferred on the local side because the
internal pipeline of the PCI MegaCore function is full.
The 64-bit extension signals shown in
pci_mt32 and pci_t32 MegaCore functions.
Adr-PAR
4
Z
Z
PCI Compiler Version 10.1
Z
shows the same transaction as in
5
BE0_L
BE0_H
6
381
D0_H
D0_L
7
D0_H
D1_H
D0_L
D1_L
8
Adr
6
D0-H-PAR
D0-L-PAR
D2_H
D2_L
Figure 3–9
781
BE1_L
D1_H
BE1_H
D1_L
9
Figure 3–8
381
D1-H-PAR
D1-L-PAR
D3_H
D3_L
10
are not applicable to the
Functional Description
BE2_L
D2_H
BE2_H
D2_L
11
with the PCI bus
781
D2-H-PAR
D2-L-PAR
12
Z
Z
000
Z
Z
3–55
13