IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 180

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Master Mode Operation
3–106
PCI Compiler User Guide
Mismatched Bus Width Burst Memory Read Master Transactions
The following description applies only to the pci_mt64 MegaCore
functions handling mismatched bus width memory read master
transactions.
Figure 3–37
master transaction. The events shown in
shown in
requests a 64-bit transaction by asserting lm_req64n. The pci_mt64
function asserts req64n on the PCI side. However, the PCI target cannot
transfer 64-bit data, and therefore does not assert ack64n in clock cycle 7
and the upper address ad[63..32] and the upper command/byte
enables cben[7..4] are invalid.
Valid data is only presented on the l_dato[31..0] bus; however,
because the PCI side is 32 bits wide and the local side is 64 bits wide, the
l_ldat_ackn and l_hdat_ackn signals toggle to indicate whether the
the low or high DWORD is being transferred on the local side. Along with
these signals, valid data is qualified with lm_ackn asserted.
1
Because the local-side master interface is 64 bits and the PCI
target is only 32 bits, these transactions always begin on 64-bit
boundaries, which results in l_ldat_ackn always asserted
first.
Figure
PCI Compiler Version 10.1
shows a 32-bit PCI and 64-bit local side burst memory read
3–31. In this transaction, the local-side master interface
Figure 3–37
are the same as those
Altera Corporation
January 2011