IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 243

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
4.
SOPC Builder will generate informational messages indicating the PCI
MegaCore function you have instantiated and the actual PCI BAR setting.
Generate the SOPC Builder System
You will now generate your SOPC system.
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You can now simulate the system using any Altera-supported third party
simulator, compile the system in the Quartus II software, and configure
an Altera device.
From the System menu, select Auto-Assign Base Addresses.
In the SOPC Builder window, click Next to display the System
Generation tab.
In the System Generation tab, turn on Simulation. Create
simulator project files.
Click Generate. Messages about the PCI MegaCore function that
was instantiated and the progress of the system generation are
displayed in the SOPC Builder message window.
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PCI Compiler Version 10.1
Among the files generated by SOPC Builder is the Quartus
II IP File (.qip). This file contains information about a
generated IP core or system. In most cases, the .qip file
contains all of the necessary assignments and information
required to process the MegaCore function or system in the
Quartus II compiler. Generally, a single .qip file is generated
for each SOPC Builder system. However, some more
complex SOPC Builder components generate a separate
.qip file. In that case, the system .qip file references the
component .qip file.
PCI Compiler User Guide
Getting Started
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