IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 282

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Interface Signals
7–14
PCI Compiler User Guide
ArbReq_n_i[N-1]
ArbGnt_n_o[N-1]
Table 7–2. PCI Arbiter Ports
Name
f
requirements. If you use the PCI constraint files as recommended, the
SOPC Builder reset signal will be assigned to the PCI reset signal and all
PCI settings will automatically be made in your Quartus II project file.
Depending on the selected clock option, you may have one or more clock
signals in your SOPC Builder system. There are two clock options (refer
to
■
■
For more information on using PCI constraint files, refer to
Using PCI Constraint File Tcl
PCI Bus Arbiter Signals
Table 7–2
present when the Altera-Provided Arbiter Internal to Device option is
selected in the PCI bus arbiter field (refer to
Reads” on page
“Value of Multiple Pending Reads” on page
If you select Shared PCI and Avalon Clocks, the resulting SOPC
Builder system will have only one clock signal, clk. This pin must be
connected to your device’s PCI clock signal and must have all of the
appropriate PCI assignments in your Quartus II project. The PCI
constraint files do not make the appropriate assignments.
If you select Independent PCI and Avalon Clocks, the resulting
SOPC Builder system will have at least two clock signals, clk and
clk_<pci_compiler_instance_name>. The latter of these signals must
be connected to your device’s PCI clock signal on your device and
must have the appropriate PCI assignments in your Quartus II
project. You can use the PCI constraint files to make all of the
appropriate PCI assignments.
Input
Output
Type
lists the PCI arbiter interface signals. These signals are only
PCI Compiler Version 10.1
Bus request inputs. These signals are asserted when the
connected agent wants to master the PCI bus. Where N is the
number of PCI devices supported by the arbiter.
Bus grant outputs. These signals are asserted when the bus is
granted to one of the attached devices. Where N is the number
of PCI devices supported by the arbiter.
6–6).
Scripts.
Description
“Value of Multiple Pending
6–6):
Altera Corporation
Appendix A,
January 2011