IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 341

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
mem_rd_64
The mem_rd_64 command performs memory read transactions with the
address provided in the command argument. This command can perform
single-cycle or burst 64-bit memory read depending on the value of the
qword argument.
■
■
io_wr
The io_wr command performs a single-cycle memory write transaction
with the address and data provided in the command arguments.
io_rd
The io_rd command performs single-cycle I/O read transactions with
the address provided in the command argument.
Syntax:
Arguments:
Syntax:
Arguments:
Syntax:
Arguments:
If the qword value is one, the command performs a single-cycle
transaction.
If the qword value is greater than one, the command performs a
burst transaction.
PCI Compiler Version 10.1
mem_rd_32(address, qword)
address
qword
io_rd(address)
address
io_wr(address, data)
address
data
Transaction address. This value must be in
hexadecimal radix.
The number
one indicates a single-cycle memory read
transaction. A value greater than one indicates a
burst transaction. This value must be an integer.
Transaction address. This value must be in
hexadecimal radix.
Transaction address. This value must be
in hexadecimal radix.
Data written during the transaction. This
value must be in hexadecimal radix.
QWORD
s read in the transaction. A
PCI Compiler User Guide
Testbench
8–11