IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 309

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10) DRCs can be held in the PCI-to-Avalon Read Response buffers, allowing them to be passed by PMWs, DRRs or
(11) If multiple PCI-to-Avalon Read Response buffers are implemented, then one DRC can pass another. Otherwise,
PMW
DRR
DWR
DRC
DWC
Table 7–14. Summary of Ordering in the Avalon-to-PCI Direction
Spec refers to the PCI Local Bus Specification, Revision 3.0, published by PCI-SIG.
Impl refers to the implementation of this passing rule in the PCI-Avalon bridge.
PMWs, DRRs, and DWRs will not pass other PMWs or DWRs since a request at the head of the Avalon-to-PCI
Command/Write Data buffer will be handled first before any subsequent requests.
Ordering logic will make sure that PCI-to-Avalon Read Completion data is not indicated as available on the PCI
side until a previous PMW or DWR is issued.
DWCs are never passed through the PCI-Avalon bridge. The PCI-Avalon bridge can only be the target of a
Configuration Write and these are never delayed.
DRRs can be held pending in the pending read logic or the Avalon
to be passed by PMWs, DWRs, or DRCs.
Avalon-MM requires that all read data be returned in the order requested. It is possible they can complete on PCI
in a different order if there are multiple Avalon
PMWs cannot pass I/O Writes or Configuration Writes (DWRs). However, since the PCI-Avalon bridge does treat
I/O Writes or Configuration Writes in a non-posted fashion, the deadlock avoidance required by the PCI
specification is not required.
DRCs cannot pass I/O Writes or Configuration Writes (DWRs). However, since the PCI-Avalon bridge does treat
I/O Writes or Configuration Writes in a non-posted fashion, the deadlock avoidance required by the PCI
specification is not required.
DWRs.
only one delayed read can be in progress at a time.
Table
No
No
No
No
Yes/ No
Spec(1) Impl(2)
7–14:
PMW
No(3)
No(3)
No(3)
No(4)
N/A(5)
Table 7–14
bridge for the Avalon-to-PCI direction. The entries in this table describe
whether a type in a row may pass a type in a column. The table uses the
following terminology: "No" means a type may not pass another type,
"Yes/No" means a type may pass the other type, but does not have to, and
"Yes" means that a type must pass another type to avoid deadlocks.
Yes
Yes/ No
Yes/ No
Yes
Yes
Spec
DRR
PCI Compiler Version 10.1
specifies the ordering rules and behavior of the PCI-Avalon
Yes(6)
No(7)
Yes(6)
Yes(6)
N/A(5)
Impl
-to-
PCI Read Response buffers.
Yes
Yes/ No
Yes/ No
Yes
Yes
Spec
DWR
No(8)
No(3)
No(3)
No(9)
N/A(5)
Impl
-to-
PCI Bypassable Read Buffer, allowing them
Yes
Yes/ No
Yes/ No
Yes/ No Yes/
Yes/ No
Spec
DRC
Yes(10)
Yes(10)
Yes(10)
No(11)
N/A(5)
Impl
Functional Description
Yes
Yes/ No
Yes/ No
Yes/ No
Yes/ No
Spec
DWC
N/A(5)
N/A(5)
N/A(5)
N/A(5)
N/A(5)
Impl
7–41