IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 22

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Compliance Summary
Compliance
Summary
10
PCI Compiler User Guide
PCI Compiler With MegaWizard Plug-in Manager Flow
This section lists the advantages and disadvantages of the PCI Compiler
with MegaWizard Plug-in Manager flow.
Advantages
■
■
■
Disadvantages
■
■
■
■
The MegaCore functions are compliant with the requirements specified in
the PCI SIG PCI Local Bus Specification, Revision 3.0 and Compliance
Checklist, Revision 3.0.
To ensure PCI compliance, Altera has performed extensive validation of
the PCI MegaCore functions. Validation includes both simulation and
hardware testing. The following simulations are covered by the
validation suite for the PCI MegaCore functions:
■
■
■
■
In addition to simulation, Altera performed extensive hardware testing
on the functions to ensure robustness and PCI compliance. The test
platforms include the Agilent E2928A PCI Bus Exerciser and Analyzer, an
Altera PCI development board with a device configured with a PCI
MegaCore function and a reference design, and PCI bus agents such as a
More control of the system feature set
Can design directly from the PCI interface to peripheral devices
Can access local-side interface to reduce clock cycles and achieve
higher bandwidth
Requires manual integration of system modules
Cannot easily use existing SOPC Builder peripherals
Requires a register transfer level (RTL) file for each instantiation
Requires significant knowledge of the PCI bus protocol
PCI-SIG checklist simulations
Applicable operating rules in Appendix C of the PCI Local Bus
Specification, Revision 3.0, including:
●
●
●
●
●
●
●
●
Local-side interface functionality
Corner cases of the PCI and local-side interface, such as random wait
state insertion
Basic protocol
Signal stability
Master and target signals
Data phases
Arbitration
Latency
Device selection
Parity
PCI Compiler Version 10.1
Altera Corporation
January 2011