IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 295

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Figure 7–8. PCI-to-Avalon Address Translation
PCI Master
Operation
Altera Corporation
January 2011
BAR0 (or 0:1)
Inside PCI MegaCore Function
BAR1
BAR2
BAR3
BAR4
BAR5
P-1
PCI Address
High
This section describes the PCI master mode operation. Because the PCI
Target-Only Peripheral mode is a subset of the PCI Master/Target
Peripheral mode, the information in the previous section also applies to
the target side of the PCI Master/Target Peripheral mode.
The PCI master mode operation applies to Avalon-to-PCI transactions.
The PCI-Avalon bridge automatically accepts Avalon-MM read and
write operations targeting the PCI Bus Access Slave port interface and
translates them into PCI master transactions. Transaction progress and
error conditions are stored in the control/status registers that can be
accessed via the control access port.
The Avalon-to-PCI address translation module (refer to
Address Translation” on page
and write requests are issued on PCI as memory, I/O, or configuration
space transactions. Except for the command used, accesses to the
different spaces operate identically. Burst transactions may even be
attempted to configuration space, but this is unusual behavior and target
devices may not operate correctly.
You have the option to make the Avalon-to-PCI address translation
module either fixed at compile time or dynamically-configured at run
time. A fixed Avalon-to-PCI address translation module is very useful for
embedded systems with very few PCI devices. If the dynamic address
translation table is used, you need to write to it using the Control
Register Access Avalon Slave port.
N N-1
Low
PCI Compiler Version 10.1
0
Selects Avalon
Matched BAR
Addresses
(BAR Specific Number of Bits)
Low Address Bits Unchanged
Hardcoded BAR Specific
7–35) controls whether Avalon-MM read
N = Number of Pass Through Bits (BAR Specific)
M = Number of Avalon Address Bits
P = Number of PCI Address Bits (64/32)
Avalon Addresses
Avalon_Addr_B0
Avalon_Addr_B1
Avalon_Addr_B2
Avalon_Addr_B3
Avalon_Addr_B4
Avalon_Addr_B5
Avalon Address
M-1
Functional Description
BAR Specific Number
of High Avalon Bits
High
“Avalon-to-PCI
N
N-1
Low
0
7–27