IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 321

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
The Avalon-to-PCI mailbox registers are readable at the addresses shown
in
information after being signaled by the corresponding bits in the PCI
interrupt status register.
Avalon-to-PCI Address Translation Table
Unless fixed mapping is used, the Avalon-to-PCI address translation
table is writable via the Control Register Access Avalon Slave
port. In effect, the translation table is writable if the Dynamic Translation
Table is selected (refer to
translation table is always readable at the same addresses.
Each entry in the PCI address translation table is always 64 bits (8 bytes)
wide, regardless of whether the system supports 64-bit PCI addressing.
64-bit addressing is supported only when the PCI bus width is 64 bits.
This ensures that the table address always has the same register
addressing regardless of PCI addressing width.
0x0900
0x0904
0x0908
0x090C
0x0910
0x0914
0x0918
0x091C
Table 7–21. Avalon-to-PCI Mailbox Registers – Address Range:
0x0900-0x091F
Address
Table
7–21. PCI Hosts use these addresses to read the mailbox
PCI Compiler Version 10.1
A2P_MAILBOX0
A2P_MAILBOX1
A2P_MAILBOX2
A2P_MAILBOX3
A2P_MAILBOX4
A2P_MAILBOX5
A2P_MAILBOX6
A2P_MAILBOX7
Name
“Avalon Configuration” on page
RO
RO
RO
RO
RO
RO
RO
RO
Access
Avalon-to-PCI mailbox 0.
Avalon-to-PCI mailbox 1.
Avalon-to-PCI mailbox 2.
Avalon-to-PCI mailbox 3.
Avalon-to-PCI mailbox 4.
Avalon-to-PCI mailbox 5.
Avalon-to-PCI mailbox 6.
Avalon-to-PCI mailbox 7.
Functional Description
Description
6–16). The
(Table
7–22.)
7–53