IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 140

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Target Mode Operation
3–66
PCI Compiler User Guide
7
8
9
Table 3–36. Single-Cycle Memory Write Target Transactions (Part 2 of 2)
Clock
Cycle
The rising edge of clock cycle 7 registers the valid data from the
l_dato
l_beno
that there is valid data on the
lt_rdyn
transferred in clock cycle 7.
lt_tsr
clock cycle. The PCI MegaCore function also deasserts
transaction. To satisfy the requirements for sustained tri-state buffers, the PCI MegaCore function
drives
The PCI MegaCore function resets all
completed the transaction. The PCI MegaCore function also tri-states its control signals.
The PCI MegaCore function deasserts
data is in the internal pipeline.
devseln
[10] is asserted to indicate a successful data transfer on the PCI side during the previous
bus, registers valid byte enables from the
bus. At the same time, the PCI MegaCore function asserts the
is asserted during clock cycle 6 and
,
ack64n
,
lt_dxfrn
trdyn
l_dato
PCI Compiler Version 10.1
, and
lt_tsr[11..0]
bus and a valid byte enable on the
lt_framen
is asserted in clock cycle 7 to signify a local-side transfer.
stopn
Event
lt_ackn
high during this clock cycle.
cben
indicating to the local side that no additional
trdyn
bus, and drives the byte enables on the
is asserted in clock cycle 7, data will be
signals because the PCI side has
,
devseln
ad
bus and drives the data on the
lt_ackn
l_beno
, and
ack64n
Altera Corporation
signal to indicate
bus. Because
January 2011
to end the